FIG. 5 shows the configuration of a monolithic ceramic capacitor relating to the present invention.
With reference to FIG. 5, the monolithic ceramic capacitor 1 includes a capacitor body 2, a first outer electrode 3, and a second outer electrode 4. The first and second outer electrodes 3 and 4 are disposed on opposed end faces of the capacitor body 2. The capacitor body 2 includes a capacitance-forming section 8 and outer layer sections 9 disposed on each of the upper or lower face of the capacitance-forming section 8. The capacitance-forming section 8 includes a plurality of internal electrodes 5 and 6 and a plurality of dielectric ceramic layers 7. The internal electrodes 5 and 6 and the dielectric ceramic layers 7 are alternately arranged.
The internal electrodes 5 and 6 are categorized into first internal electrodes 5 and second internal electrodes 6. Each first internal electrode 5 and each second internal electrode 6 are paired to form a capacitance therebetween. The first internal electrodes 5 are electrically connected to the first outer electrode 3 and the second internal electrodes 6 are electrically connected to the second outer electrode 4.
In the monolithic ceramic capacitor 1, the dielectric ceramic layers 7 and outer layer sections 9 disposed in the capacitance-forming section 8 are usually made of the same dielectric ceramic material.
The monolithic ceramic capacitor 1 is manufactured as follows: the capacitor body 2 which is unfired and which includes the internal electrodes 5 and 6, the dielectric ceramic layers 7, and the outer layer sections 9 are prepared and then fired; a conductive paste is applied onto both end faces of the fired capacitor body 2; and the first and second outer electrodes 3 and 4 are formed by baking the resulting conductive paste.
In the monolithic ceramic capacitor 1, the thermal expansion coefficient of the dielectric ceramic material, which is used for forming the dielectric ceramic layers 7 and the outer layer sections 9, is different from that of the internal electrodes 5 and 6 and that of the outer electrodes 3 and 4. Therefore, a residual stress is generated in the capacitor body 2 during the firing step for sintering the capacitor body 2 and also in the baking step for forming the outer electrodes 3 and 4. In particular, a tensile stress 11 is concentrated on an end portion 10 of each of the outer electrodes 3 and 4 as indicated by a dotted arrow in FIG. 5.
Under these circumstances, if a stress is generated in the capacitor body 2 by an external factor such as mounting, the cyclic application of heat or the warpage of a wiring board (not shown) on which the monolithic ceramic capacitor 1 is mounted, the stress is applied to the end portion 10 of each of the outer electrodes 3 and 4 in addition to the tensile stress 11; hence, cracks are formed in the end portion 10. The cracks extend from the end portion 10 in the direction indicated by an arrow 12.
Patent Documents 1 and 2 disclose techniques in which the formation of such cracks is prevented by improving the configuration of outer layer sections 9.
In particular, Patent Document 1 discloses that a dielectric ceramic material for forming these outer layer sections 9 has a thermal expansion coefficient that is 0.2×10−6/° C. to 1×10−6/° C. less than that of the dielectric ceramic material used for forming dielectric ceramic layers 7 included in capacitance-forming section 8 and these outer layer sections 9 have a thickness of 20 to 200 μm. In this configuration, these outer layer sections 9 have a thermal expansion coefficient less than that of this capacitance-forming section 8; hence, the compressive stresses applied to these outer layer sections 9 and the compressive stresses applied to end portions of outer electrode 3 and 4 are increased by the shrinkage of the capacitance-forming section 8 due to cooling. This prevents the formation of cracks.
Patent Document 2 discloses that the outermost layer of each outer layer section 9 is made of a dielectric ceramic material with high mechanical strength and a second layer located inside the outermost layer is porous. In this configuration, the second layer absorbs the difference in shrinkage between the outermost layer of the outer layer section 9 and a capacitance-forming section 8 and the formation of cracks is prevented by the outermost layer, which has high a mechanical strength.
According to the technique disclosed in Patent Document 1, the difference in thermal expansion coefficient between the outer layer sections 9 and the outer electrodes 3 and 4 is large and the tensile stress 11 applied to the end portion 10 of each of the outer electrodes 3 and 4 is large. This can cause cracks.
Even in the techniques disclosed in Patent Documents 1 and 2, low-stress cycles such as heat cycles can cause fatigue failure, which causes cracks. These cracks can propagate in the outer layer sections 9 to reach the internal electrodes 5 and 6 as indicated by the arrow 12 in FIG. 5. This causes short circuits and/or property deterioration such as a reduction in capacitance in the monolithic ceramic capacitor 1.
Patent Document 1: Japanese Unexamined Patent Application Publication No. 3-136308
Patent Document 2: Japanese Unexamined Patent Application Publication No. 2-86109